1. Field of the Invention
The present invention relates to a phase-locked signal generator for generating a clock signal phase-locked with a trigger signal and a level comparator used for the phase-locked signal generator.
2. Related Background Art
In a video memory for storing, e.g., a video signal in a semiconductor memory, a sampling clock synchronized with a horizontal synchronization signal of an input video signal must be formed. For this purpose, a phase-locked signal generator having an arrangement of FIG. 1 is used in a conventional system. An operation of the phase-locked signal generator in FIG. 1 will be described with reference to FIG. 2.
When an input terminal A is set at H level, a square wave pulse having a period of 2.tau. is oscillated and appears at an output terminal B by means of a NAND gate 15 and a delay line 17 having a delay time .tau. through an inverter 16. When a synchronization trigger signal set at L level within a predetermined pulse width T1 from a leading edge (or trailing edge) of the horizontal synchronization signal is input to the input terminal A, an output from the NAND gate 15 is forcibly set at H level within the pulse width T1, and the output terminal B is set at "L" level. Upon a lapse of the pulse width T1 at the input terminal A, the output from the NAND gate 15 goes to L level (therefore the output terminal B is set at H level), and a square wave pulse having the period 2.tau. is oscillated and output at the output terminal B. If the pulse width T1 and the delay time .tau. are constants, a sampling clock signal having the period of 2.tau. synchronized with the horizontal synchronization signal appears at the output terminal B.
In a conventional laser beam printer (to be referred to as an LBP hereinafter), a beam deflection position and a timing of a beam modulated with an image signal are very important factors. The beam deflection position and the beam modulation timing largely influence quality of the resultant image. For this reason, a detection signal from a beam position detection unit for detecting a beam deflection position and a clock input to a laser beam modulator must be in phase. For this purpose, a synchronization oscillator almost free from jitter is required to generate this clock.
A conventional arrangement for obtaining a phase-locked oscillation signal almost free from jitter is shown in FIG. 3. As shown in FIG. 3, a clock having a frequency which is N times a necessary fundamental frequency (f0) is generated and is frequency-divided into 1/N, so that a jitter amount for the synchronization pulse is set to 1/N the fundamental clock period.
Referring to FIG. 3, a beam position detection unit 21 outputs a detection signal for a beam representing a beam deflection position. A clock oscillator (OSC) 22 oscillates a clock having a frequency which is N times the fundamental clock frequency f0. A D flip-flop (D-FF) 23 generates a reset pulse for synchronously resetting a 1/N counter 25 and a 1/n counter 24 (both will be described in detail below) in response to an N-time clock by using the detection signal and a time error of 1/Nf0 or less. The 1/n counter 24 determines generation of a pulse representing that the detection signal is detected and the synchronized fundamental clock has been generated, and at the same time determines a period for outputting the synchronized fundamental clock. The 1/N counter 25 is reset in response to the synchronization pulse as an output from the D-FF 23 and frequency-divides the N-time clock into 1/N.
An operation of the conventional arrangement described above will be described with reference to FIG. 4.
Referring to FIG. 4, when a synchronization pulse b representing a beam deflection position rises during a time interval between time t1 and time t2, the 1/N counter 25 is reset to stop oscillation of the fundamental clock f0, and counting of the 1/n counter 24 is started. The 1/n counter 24 counts a desired period from the input of the synchronization pulse to generation of the fundamental clock and generates a reset pulse e at time t3, thereby resetting the D-FF 23. An output from the D-FF 23 is inverted in accordance with the reset pulse e. The 1/n counter 24 stops counting from time t4. The 1/N counter 25 starts counting and outputs a clock having the frequency f0. Since a jitter amount of the fundamental clock f and the detection signal b from time t4 is a maximum of (t2 -t1) and can be smaller than 1/N or less of the period of the fundamental clock.
In the conventional arrangement shown in FIG. 1, however, since frequency precision of the synchronization clock signal is determined by the delay time .tau. of the delay line 17, expensive parts such as a pulse delay line and adjustment such as selection of a tap or the like are required. In addition, since the threshold value of the NAND gate 15 is not generally stabilized by a temperature and a power source voltage, it is difficult to stably set the threshold level to a predetermined value.
In the conventional arrangement shown in FIG. 3, the N-time clock is required to obtain the necessary fundamental clocks f0. According to the knowledge of the present inventor, although a fundamental clock in an LBP having a resolution of 2400 DPI (dot per inch) about 1.55 MHz, a fundamental clock in a 600-DPI LBP has a frequency of 9.69 (=1.55.times.(600/240).sup.2) MHz, i.e., in proportion to a square of the resolution, because horizontal and vertical resolution components must be balanced. Even if a jitter amount is allowed up to 1/8 the fundamental clock period, an initial oscillation frequency is 12.4 MHz in a 2400-DPI LBP, but an initial oscillation frequency requires a 77.5-MHz oscillator in a 600-DPI LBP.
When an oscillation signal having such a high frequency is used, the following problems are posed.
(1) It is very difficult to obtain a quartz crystal oscillator for oscillating a fundamental wave of 77.5 MHz as an initial oscillation frequency.
(2) In a quartz crystal oscillator using an overtone mode such as 3-time overtone mode, since a tuner such as a coil or a capacitor is required, a total cost is undesirably increased by adjustment and an additional circuit.
(3) Since the oscillation frequency is very high, the 77.5-MHz signal serves as an unnecessary radiation component for other peripheral circuits and peripheral equipment, thereby adversely affecting the operation.
(4) It is very difficult to perform accurate operations in gate arrays or the like because an operating frequency is high.
On the other hand, in a television signal color encoder such as an NTSC color encoder, since B-Y and R-Y signals are modulated with 0.degree. and 90.degree., respectively, carrier signals (3.58 MHz) having phases of 0.degree. and 90.degree. are required.
Conventional carrier signals having the phases of 0.degree. and 90.degree. are formed by a signal obtained by digitally counting down a clock signal having a high frequency into 1/N, as shown in FIG. 5. FIG. 5 is a block diagram showing an arrangement for forming the carrier signals having phases of 0.degree. and 90.degree., and FIG. 6 is a timing chart showing an operation of the circuit in FIG. 5.
Referring to FIG. 5, a counter 5 counts down a clock CLK into 1/N. In this case, N is selected so that a frequency of a counter output becomes 3.58 MHz.times.2. D-flip-flops (D-FFs) 6 and 7 receive a positive output (a) and a negative output (b) as trigger pulses from the counter 5. The D-FFs 6 and 7 output carrier signals having 0.degree. and 90.degree., respectively. Timings of the above signals are shown in FIG. 6.
Another method of forming carrier signals having phases of 0.degree. and 90.degree. is to use a phase-locked oscillator. FIG. 7 is a block diagram of a phase-locked oscillator. Referring to FIG. 7, a phase comparator 1 compares a phase of a reference signal (c) and VO of an output from a VCO (voltage-controlled oscillator) 3 and outputs a phase error (d). A low-pass filter (LPF) 2 smoothes a phase error output from the phase comparator 1. The VCO 3 changes an output frequency in accordance with the phase error voltage (e) smoothed by the LPF 2. In order to obtain a 90.degree. signal from the output VO from the VCO 3 with respect to the reference signal, the phase comparator 1 is designed so that zero phase error is output with a 90.degree. phase difference.
FIG. 8 is a timing chart showing a case wherein zero phase error is obtained with the phase of 90.degree.. The output VO and the phase error (d) are set in a 90.degree. phase state with respect to the phase of the reference signal (c). When the output from the phase comparator 1 is smoothed by the LPF 2, a phase error voltage (e) has an intermediate level. At this time, the phase error voltage (e) is set at a level (e)-1, and the VCO is oscillated at the same frequency as the reference signal. The phase of the output from the VCO 3 is advanced from the reference signal (c) as indicated by VO'. Control is performed such that the output from the phase comparator 1 becomes an output (d)', the level of the phase error voltage (e) is increased to (e)-2, the oscillation frequency of the VCO 3 is increased, and the phase of the output from the VCO 3 is set to 90.degree. with respect to the reference signal (c). When the output from the VCO 3 becomes VO", a reverse operation is performed. Control is performed such that the phase error voltage becomes reduced to (e)-3, the oscillation frequency of the VCO 3 is decreased, and the output from the VCO 3 has a 90.degree. phase difference with respect to the reference signal (c).
In the color signal encoder, however, color misregistration occurs even if the phase difference of an input carrier is shifted from 90.degree. by .+-.1.degree. to 2.degree.. Therefore, the following problems are posed by the conventional arrangement.
In the count-down scheme (FIG. 5),
(1) since the carrier frequency is 3.58 MHz (NTSC scheme), a clock must be a high-frequency clock so as to stably obtain a high-precision 90.degree. phase difference; and PA0 (2) two carrier signal inputs are required for a color encoder. PA0 (3) Although the phase is ideally locked with a phase error of 90.degree., another phase error different from that of the input signal occurs due to variations in elements constituting a circuit, and an error occurs in the locked phase.
In the phase-locked oscillator (FIG. 7),